SMJ320C80 Datasheet, PDF (77/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

read cycles (continued)
State
Col A
Col B
Col C
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
r1
r2
r3
r6
col
col
col
col
r1
c1
c2
c1
c2
c1
c2
5
Cycle Type
Row
PAC PAC PAC Idle
Col A Col B Col C
A
B
C
TRG/CAS
W
D[63:0]
A
B
C
DBEN
0 For Normal Reads, 1 For PDPT Reads
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
A
B
C
Figure 59. Nonpipelined 1-Cycle/Column Read-Cycle Timing
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