SMJ320C80 Datasheet, PDF (117/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SDRAM write cycles (continued)
State
r1
r2
r3
Col Pipe
CLKOUT
SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
r5
r6 rspin
col col
col
col
col
col
r1
Col A
c1
Col B
c1
Col C
c1
Col D
c1
CT[2:0]
2, 3
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Idle DCAB
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
Row
Col A (Col B) Col C
(Col D)
A
B
C
D
A, B
C, D
A
B
C
D
DBEN
DDIN
Command
ACTV
WRT
WRT
Figure 93. SDRAM Burst-Length 2 Write-Cycle Timing
DCAB
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