SMJ320C80 Datasheet, PDF (107/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM-type cycles
The SDRAM-type cycles support the use of SDRAM, SGRAM, or SVRAM devices for single-cycle memory
accesses. While SDRAM cycles use the same state sequences as DRAM cycles, the memory-control signal
transitions are modified to perform SDRAM command cycles. The supported SDRAM commands are:
DCAB
Deactivate (precharge) all banks
ACTV
Activate the selected bank and select the row
READ
Input starting column address and start read operation
WRT
Input starting column address and start write operation
MRS
Set SDRAM mode register
REFR
Auto-refresh cycle with internal address
SRS
Set special register (color register)
BLW
Block write
SDRAM cycles begin with an activate (ACTV) command followed by the requested column accesses. When
a memory-page change occurs, the selected bank is deactivated with a DCAB command.
The SMJ320C80 supports CAS latencies of 2 or 3 cycles and burst lengths of 1 or 2. These are selected by the
CT code input at the start of the access.
The column pipelines for SDRAM accesses are shown in Figure 85. Idle cycles can occur after necessary
column accesses have completed or between column accesses due to “bubbles” in the TC data flow pipeline.
The pipeline diagrams show the pipeline stages for each access type and when the CAS/DQM signal
corresponding to the column access is activated.
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