SMJ320C80 Datasheet, PDF (79/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles (continued)
State
r1 r2 r3 r4 r5 r6 col col col col col col^† col ci^‡ col col col r1
Col A
c1 c2 c3
Col B
c1 c2 c3 c3
Col C
c1 c2 c3
CLKOUT
CT[2:0]
7
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Idle
PAC
RL
A[31:0]
Row
Column A
Column B
Column C
RAS
CAS/DQM[7:0]
A
B
C
DSF
TRG/CAS
W
D[63:0]
A
B
C
DBEN
0 For Normal Reads, 1 For PDPT Reads
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
A
B
C
† _{Wait state inserted by external logic (example)}
‡ _{Internally generated pipeline bubble (example)}
Figure 61. 3-Cycle/Column Read-Cycle Timing
write cycles
Write cycles transfer data from the ’C80 to external memory. These cycles can occur as a result of a packet
transfer, a DEA request, or an MP data cache write-back. During the cycle TRG/CAS is held high, W is driven
low after the fall of RAS to enable early-write cycles, and DDIN is high so that data transceivers drive toward
memory. The TC drives data out on D[63:0] and indicates valid bytes by activating the appropriate CAS/DQM
strobes. During peripheral device packet transfers, DBEN remains high and D[63:0] is placed in high impedance
so that the peripheral device can drive data into the memory.
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