SMJ320C80 Datasheet, PDF (63/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
TC architecture
The transfer controller (TC) is a combined memory controller and DMA (direct memory access) machine. It
handles the movement of data within the ’C80 system as requested by the master processor, parallel
processors, and external devices. The transfer controller performs the following data movement and memory
control functions:
D MP and PP instruction cache fills
D MP data-cache fills and dirty block write-back
D MP and PP direct external accesses (DEAs)
D MP and PP packet transfers
D Externally initiated packet transfers (XPTs)
D Shift register transfer (SRT) packet transfers for updating VRAM-based frame buffers
D DRAM refresh
D Host bus request
TC functional block diagram
Figure 46 shows a functional block diagram of the transfer controller. Key features of the TC include:
D Crossbar interface
– 64-bit data path
– Single-cycle access
D External memory interface
– 4G-Byte address range
– Programmable:
bus size: 8-, 16-, 32-, or 64-bits
page size
bank size
address multiplexing
cycle timing
block-write mode
bank priority
– Big- or little-endian operation
D Cache, VRAM, refresh controller
– Programmable refresh rate
– VRAM block-write support
D Independent Src and Dst addressing
– Autonomous addressing based on packet-transfer parameters
– Data read and write at different rates
– Numerous data merging and alignment functions performed during transfer
D Intelligent request prioritization
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