SMJ320C80 Datasheet, PDF (72/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
memory cycles (continued)
rhiz
bus request
always
bus release
idle or abort
r1
r9
always
always
r8
r2
any cycle
wait
r3
drn
r7
r4
always
r5
MRS or DCAB
!MRS & !DCAB
spin
r6
spin
rspin
col access
wait
col access
Column Pipeline
Figure 56. Memory Cycle State Diagram
72
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