SMJ320C80 Datasheet, PDF (78/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles (continued)
State
Col A
Col B
Col C
r1
r2
r3
r5
r6 col col col col^† col ci^‡ col col
r1
c1 c2
c1 c2 c2
c1 c2
CLKOUT
CT[2:0]
6
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Idle
PAC
RL
A[31:0]
Row
Col A
Col B
Col C
RAS
CAS/DQM[7:0]
A
B
C
DSF
TRG/CAS
W
D[63:0]
DBEN
A
B
C
0 For Normal Reads, 1 For PDPT Reads
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
A
B
C
† _{Wait state inserted by external logic (example)}
‡ _{Internally generated pipeline bubble (example)}
Figure 60. 2-Cycle/Column Read-Cycle Timing
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