SMJ320C80 Datasheet, PDF (13/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Terminal Functions (Continued)
TERMINAL
NAME
TYPE^†
DESCRIPTION
VIDEO INTERFACE
CAREA0, CAREA1
O
Composite area. CAREA0 and CAREA1 define a special area such as an overscan boundary. This area
represents the logical OR of the internal horizontal and vertical area signals.
CBLNK0/VBLNK0,
CBLNK1/VBLNK1
Composite blanking/vertical blanking. Each of CBLNK0/VBLNK0 and CBLNK1/VBLNK1 provides one of
two blanking functions, depending on the configuration of the CSYNC/HBLNK pin:
Composite blanking disables pixel display/capture during both horizontal and vertical retrace periods
and is enabled when CSYNC is selected for composite-sync video systems.
O
Vertical blanking disables pixel display/capture during vertical retrace periods and is enabled when
HBLNK is selected for separate-sync video systems.
Following reset, CBLNK0/VBLNK0 and CBLNK1 / VBLNK1 are configured as CBLNK0 and CBLNK1,
respectively.
CSYNC0/HBLNK0,
CSYNC1/HBLNK1
I/O/Z
Composite sync/horizontal blanking. CSYNC0/HBLNK0 and CSYNC1/HBLNK1 can be programmed for
one of two functions:
Composite sync is for use on composite-sync video systems and can be programmed as an input,
output, or high-impedance signal. As an input, the ’C80 extracts horizontal and vertical sync information
from externally generated active-low sync pulses. As an output, the active-low composite-sync pulses
are generated from either external HSYNC and VSYNC signals or the ’C80’s internal video timers. In
the high-impedance state, the pin is neither driven nor allowed to drive circuitry.
Horizontal blank disables pixel display/capture during horizontal retrace periods in separate-sync
video systems and can be used as an output only.
Immediately following reset, CSYNC0/HBLNK0 and CSYNC1/HBLNK1 are configured as
high-impedance CSYNC0 and CSYNC1, respectively.
FCLK0, FCLK1
I
Frame clock. FCLK0 and FCLK1 are derived from the external video system’s dotclock and are used to
drive the ’C80 video logic for frame timer 0 and frame timer 1.
HSYNC0,
HSYNC1
I/O/Z
Horizontal sync. HSYNC0 and HSYNC1 control the video system. They can be programmed as input,
output, or high impedance signals. As an input, HSYNC synchronizes the video timer to externally
generated horizontal sync pulses. As an output, HSYNC is an active-low horizontal sync pulse generated
by the ’C80 on-chip frame timer. In the high-impedance state, the pin is not driven, and no internal
synchronization is allowed to occur. Immediately following reset, HSYNC0 and HSYNC1 are in the
high-impedance state.
SCLK0, SCLK1
Serial data clock. SCLK0 and SCLK1 are used by the ’C80 shift register transfer (SRT) controller to track
I
the VRAM tap point when using midline reload. SCLK0 and SCLK1 should be the same signals that clock
the serial register on the VRAMs controlled by frame timer 0 and frame timer 1, respectively.
VSYNC0,
VSYNC1
I/O/Z
Vertical sync. VSYNC0 and VSYNC1 control the video system. They can be programmed as inputs,
outputs, or high-impedance signals. As inputs, VSYNCx synchronize the frame timer to externally
generated vertical-sync pulses. As outputs, VSYNCx are active-low vertical-sync pulses generated by the
’C80 on-chip frame timer. In the high-impedance state, the pin is not driven and no internal synchronization
is allowed to occur. Immediately following reset, VSYNCx is in the high-impedance state.
VSS^¶
VDD^¶
POWER
I
Ground. Electrical ground inputs
I
Power. Nominal 3.3-V power supply inputs
MISCELLANEOUS
NC
No connect serves as an alignment key or is for factory use and must be left unconnected.
† _{I = input, O = output, Z = high-impedance}
‡ _{This pin has an internal pullup and can be left unconnected during normal operation.}
§ _{This pin has an internal pulldown and can be left unconnected during normal operation.}
¶ _{For proper operation, all VDD and VSS pins must be connected externally.}
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