SMJ320C80 Datasheet, PDF (45/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP data-unit architecture (continued)
The PP’s ALU can be split into one 32-bit ALU, two 16-bit ALUs, or four 8-bit ALUs. Figure 38 shows the multiple
arithmetic data flow for the case of a four 8-bit split of the ALU (called multiple-byte arithmetic). The ALU
operates as independent parallel ALUs where each ALU receives the same function code.
32
mf Register
Rotate
Clear
8
A
BC
C-Out C-IN
8
C-IN
Logic
4
Expander (Replicate)
8
8
A
BC
C-Out C-IN
8
C-IN
Logic
A
BC
C-Out C-IN
8
C-IN
Logic
8
sr(C)
A
BC
C-Out C-IN
8
C-IN
Logic
C, Z,
S, or
E
C, Z,
S, or
E
C, Z,
S, or
E
C, Z,
S, or
E
Figure 38. Multiple-Byte Arithmetic Data Flow
PP multiplier
The PP’s hardware multiplier can perform one 16x16 multiply with a 32-bit result or two 8x8 multiplies with two
16-bit results in a single cycle. A 16x16 multiply can use signed or unsigned operands as shown in Figure 39.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XXXXXXXXXXXXXXXXS
Signed Input
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
Signed × Signed Result
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XXXXXXXXXXXXXXXX
Unsigned Input
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unsigned × Unsigned Result
Figure 39. 16 x 16 Multiplier Data Formats
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