SMJ320C80 Datasheet, PDF (81/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

write cycles (continued)
State
r1
Col A
Col B
Col C
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
r2
r3
r6 rspin rspin col
col
ci^†
col
r1
c1
c1
c1
5
Cycle Type
Row
PAC PAC Idle PAC
Col A Col B
Col C
A
B
C
A
B
C
0 For Normal Write, 1 For PDPT Write
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
A
B
C
† _{Internally generated pipeline bubble (example)}
Figure 63. Nonpipelined 1-Cycle/Column Write-Cycle Timing
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