SMJ320C80 Datasheet, PDF (11/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Terminal Functions
TERMINAL
NAME
TYPE^†
DESCRIPTION
LOCAL MEMORY INTERFACE
A31–A0
O
Address bus. A31–A0 output the 32-bit byte address of the external memory cycle. The address can be
multiplexed for DRAM accesses.
AS2–AS0
I
Address-shift selection. AS2–AS0 determine how the column address appears on the address bus. Eight
shift values are supported, including zero.
BS1–BS0
I
Bus size selection. BS1–BS0 indicate the bus size of the memory or other devices being accessed,
allowing dynamic bus sizing for data buses less than 64 bits wide.
CT2–CT0
I
Cycle timing selection. CT2–CT0 signals determine the timing of the current memory access.
D63–D0
I/O Data bus. D63–D0 transfer up to 64 bits of data per memory cycle into or out of the ’C80.
DBEN
O
Data-buffer enable. DBEN drives the active-low output enables of bidirectional transceivers that can be
used to buffer input and output data on D63–D0.
DDIN
O
Data direction indicator. DDIN indicates the direction of the data that passes through the transceivers.
When DDIN is low, the transfer is from external memory into the ’C80.
FAULT
I
Fault. FAULT is driven low by external circuitry to inform the ’C80 that a fault has occurred on the current
memory row access.
PS3–PS0
I
Page size indication. PS3–PS0 indicate the page size of the memory device(s) being accessed by the
current cycle. The ’C80 uses this information to determine when to begin a new row access.
READY
I
Ready. READY indicates that the external device is ready to complete the memory cycle. READY is driven
low by external circuitry to insert wait states into a memory cycle.
RL
O
Row latch. The high-to-low transition of RL can be used to latch the valid 32-bit byte address that is present
on A31–A0.
RETRY
Retry. RETRY is driven low by external circuitry to indicate that the addressed memory is busy. The ’C80
I
memory cycle is rescheduled.
STATUS5–STATUS0
O
Status code. At row time, STATUS5–STATUS0 indicate the type of cycle being performed. At column time,
they identify the processor and type of request that initiated the cycle.
UTIME
User-timing selection. UTIME causes the timing of RAS and CAS/DQM7–CAS/DQM0 to be modified so
I
that custom memory timings can be generated. During reset, UTIME selects the endian mode in which the
’C80 operates.
DRAM, VRAM, AND SDRAM CONTROL
CAS/DQM7–
CAS/DQM0
Column-address strobes. CAS/DQM7–CAS/DQM0 drive the CAS inputs of DRAMs and VRAMs, or the
O
DQM input of synchronous dynamic random-access memories (SDRAMs). The eight strobes provide
byte-write access to memory.
DSF
O
Special function. DSF selects special VRAM functions such as block-write, load color register, split-register
transfer, and synchronous graphics random-access memory (SGRAM) block write.
RAS
O
Row-address strobe. RAS drives the RAS inputs of DRAMs, VRAMs, and SDRAMs.
TRG/CAS
O
Transfer/output enable or column-address strobe. TRG/CAS is used as an output enable for DRAMs and
VRAMs, and also as a transfer enable for VRAMs. TRG/CAS also drives the CAS inputs of SDRAMs.
W
O
Write enable. W is driven low before CAS during write cycles. W controls the direction of the transfer during
VRAM transfer cycles.
† _{I = input, O = output, Z = high-impedance}
‡ _{This pin has an internal pullup and can be left unconnected during normal operation.}
§ _{This pin has an internal pulldown and can be left unconnected during normal operation.}
¶ _{For proper operation, all VDD and VSS pins must be connected externally.}
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