SMJ320C80 Datasheet, PDF (26/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP cache registers
The ILRU and DLRU registers track least-recently-used (LRU) information for the sixteen instruction-cache and
sixteen data-cache blocks. The ITAGxx registers contain block addresses and the present flags for each
sub-block. DTAGxx registers are identical to ITAGxx registers but include dirty bits for each sub-block. Figure 17
shows the cache registers.
33
10
MRU
2222
9876
NMRU NLRU
Set 3
22
54
LRU
22
32
MRU
ILRU (0x0300)
DLRU (0x0500)
2 2 1 1 1111 1 1 1 1
1 0 9 8 7654 3 2 1 0
NMRU NLRU LRU MRU NMRU NLRU
Set 2
Set 1
98
LRU
76 5 4 3 2
MRU NMRU NLRU
Set 0
10
LRU
ITAG0–ITAG15 (0x0200–0x020F)
33
10
2
9
2
8
2
7
2 2222
6 5432
2
1
2
0
1
9
1 1111 1
8 7654 3
1
2
1
1
1
0
9
87
6
5
4
3
2 10
22-Bit Cache Tag Address
P
P
P
P
3
2
1
0
Sub-Block
DTAG0–DTAG15 (0x0400–0x040F)
33
10
2
9
2
8
2
7
2
6
2222
5432
2
1
2
0
1
9
1 1111 1
8 7654 3
1
2
1
1
1
0
9
87
6
5
4
3
2 10
22-Bit Cache Tag Address
PDPD P D P D
3
2
1
0
Sub-Block
MRU
NMRU
NLRU
Most-recently-used
Next most-recently-used
Next least-recently-used
LRU
P
D
Least-recently-used
Sub-block present
Sub-block dirty
mru, nmru, nlru, and lru have the value 0, 1, 2, or 3 representing the block number and are mutually exclusive for each set.
Figure 17. Cache Registers
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