SMJ320C80 Datasheet, PDF (25/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
packet-transfer request (PKTREQ) register (0x000D)
PKTREQ controls the submission and priority of packet-transfer requests as shown in Figure 15. It also
indicates that a packet transfer is currently active.
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Reserved
I FSQP
I Immediate (urgent) priority selected
F High (foreground) priority selected
S Suspend packet transfer
Q Packet transfer queued; read only
P Submit packet-transfer request
Figure 15. PKTREQ Register
memory-fault registers
The five read-only memory-fault registers contain information about memory address exceptions, as shown in
Figure 16.
FLTOP
(0x0010)
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Dest
Reserved
K
SZ i d x r
Reserved
Block
FLTTAG
(0x0011)
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
22-Bit Cache Tag Address
PDPDPDPD
31
FLTADR
(0x0012)
FLTDTH
(0x0013)
FLTDTL
(0x0014)
3
2
1
0
Sub-Block
0
Faulting Address Accessed by the Instruction
Faulting Write Most-Significant-Data Word
Faulting Write Least-Significant-Data Word
Dest
K
SZ
Destination Register Number
Kind of Operation:
00 – load
01 – unsigned load
10 – store
11 – cache flush/clean
Size of Data:
00 – 8-bit
01 – 16-bit
10 – 32-bit
11 – 64-bit
i
d
x
r
Block
P
D
MP icache fault
MP dcache fault
DEA Fault
Modified return sequence
Faulting block number
Sub-block is present.
Dirty bit set
Figure 16. Memory-Fault Registers
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