SMJ320C80 Datasheet, PDF (84/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
load-color-register cycles
Load-color-register (LCR) cycles are used to load a VRAM’s color register prior to performing a block-write. LCR
cycles are supported only on 64-bit data buses. An LCR cycle closely resembles a normal write cycle because
it writes into a VRAM. The difference is that the DSF output is high at both the fall of RAS and the fall of
CAS/DQM. Also, because the VRAM color register is a single location, only one column access occurs.
The row address that is output by the TC is used for bank-decode only. Normally, all VRAM banks should be
selected during an LCR cycle because another LCR cycle cannot occur when a block-write memory-page
change occurs. The column address that is output during an LCR is likewise irrelevant because the VRAM color
register is the only location written. All CAS/DQM strobes are active during an LCR cycle.
If exception support for a given bank is enabled, the EXCEPT [1:0] inputs are sampled during LCR column states
and must be at valid levels. A retry code (EXCEPT [1:0] = 10) at column time has no effect, however, because
only one column access is performed.
If the BW field of the configuration cache entry for the given bank indicates that the addressed memory supports
only simulated block-writes, the LCR cycle will be changed into a normal write cycle at the start of the simulated
block-write.
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