SMJ320C80 Datasheet, PDF (23/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
interrupt-enable (IE) register (0x0006)
The IE register contains enable bits for each of the interrupts/traps as shown in Figure 11. The
global-interrupt-enable (ie) bit and the appropriate individual interrupt-enable bit must be set in order for an
interrupt to occur.
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
p x x b p pm
e43pbc i
pppp im
3210o f
x
2
x
1
ti
f
1
f
0
f
x
f
u
f
o
fz fi
ie
pe PP error
x4 External interrupt 4 (LINT4)
x3 External interrupt 3 (EINT3)
bp Bad packet transfer
pb Packet transfer busy
pc Packet transfer complete
mi MP message interrupt
p3 PP3 message interrupt
p2 PP2 message interrupt
p1 PP1 message interrupt
p0 PP0 message interrupt
io Integer overflow
mf Memory fault
x2 External interrupt 2 (EINT2)
x1 External interrupt 1 (EINT1)
ti MP timer interrupt
Figure 11. IE Register
f1 Frame-timer 1 interrupt
f0 Frame-timer 0 interrupt
fx Floating-point inexact
fu Floating-point underflow
fo Floating-point overflow
fz Floating-point divide-by-zero
fi Floating-point invalid
ie Global-interrupt enable
interrupt-pending (INTPEN) register (0x0004)
The bits in INTPEN register show the current state of each interrupt/trap. Pending interrupts do not occur unless
the ie bit and corresponding interrupt-enable bit are set. Software must write a 1 to the appropriate INTPEN bit
to clear an interrupt. Figure 12 shows the INTPEN register locations.
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
p x x b p pm
e43pbc i
pppp im
3210o f
x
2
x
1
ti
f
1
f
0
f
x
f
u
f
o
fz fi
pe PP error
x4 External interrupt 4 (LINT4)
x3 External interrupt 3 (EINT3)
bp Bad packet transfer
pb Packet transfer busy
pc Packet transfer complete
mi MP message interrupt
p3 PP3 message interrupt
p2 PP2 message interrupt
p1 PP1 message interrupt
p0 PP0 message interrupt
io Integer overflow
mf Memory fault
x2 External interrupt 2 (EINT2)
x1 External interrupt 1 (EINT1)
ti MP timer interrupt
Figure 12. INTPEN Register
f1 Frame-timer 1 interrupt
f0 Frame-timer 0 interrupt
fx Floating-point inexact
fu Floating-point underflow
fo Floating-point overflow
fz Floating-point divide-by-zero
fi Floating-point invalid
ie Global-interrupt enable
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