SMJ320C80 Datasheet, PDF (140/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
data input timing (see Figure 115)
The following general timing parameters apply to the D[63:0] inputs unless otherwise specifically given. The
value n as used in the parameters represents the integral number of half cycles between the transitions of the
output and input in question.
NO
PARAMETER
MIN MAX
34 ta(CKOH-DV) Access time, CLKOUT high to D[63:0] valid
ntH–5.3
35 ta(CKOL-DV) Access time, CLKOUT low to D[63:0] valid
ntH–6.5
36 tsu(DV-CKOH) Setup time, D[63:0] valid to CLKOUT no longer low
6.1
37 tsu(DV-CKOL) Setup time, D[63:0] valid to CLKOUT no longer high
6.1
38 th(CKOL-DV) Hold time, D[63:0] valid after CLKOUT low
2
39 th(CKOH-DV) Hold time, D[63:0] valid after CLKOUT high
2
40 ta(OUTV-DV)
Access time, output valid to D[63:0] inputs valid A[31:0], CAS/DQM[7:0]^†,
STATUS[5:0], RL
DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W
ntH–7
ntH–6.5
41 th(OUTV-DV)^‡ Hold time, D[63:0] valid after output valid RAS, CAS/DQM[7:0], A[31:0]
3
† _{Except CAS/DQM[7:0] during nonuser-timed 2-cycle/column accesses}
‡ _{Applies to RAS, CAS/DQM[7:0], and A[31:0] transitions that occur on CLKOUT edge coincident with input data sampling}
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
tH
tH
tH
tH
tH
tH
tH
tH
tH
tH
tH
tH
CLKOUT
38
36
34
39
37
35
D[63:0]
41
40
Output
Figure 115. Data-Input Timing
140
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