SMJ320C80 Datasheet, PDF (118/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
special register set cycles
Special register set (SRS) cycles are used to program control registers within an SVRAM or SGRAM. The ’C80
only supports programming of the color register for use with block-writes. The cycle is similar to a single
burst length 1 write cycle but DSF is driven high. The values output on the ’C80 address bits cause the color
register to be selected as shown in Figure 94.
SDRAM Address Pin BS
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDRAM Function
0
0
0
LC
LM
LS
Stop Register
SMJ320C80 Output Value
0
0
0
1
0
0
0
0
0
0
State
Col Pipe
Figure 94. Special-Register-Set Value
r1
r2
r3
r6
rspin
rspin
col
r1
c1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Command
0xx
Cycle Type
Row
PAC
SRS
Color
SRS
Figure 95. SDRAM SRS-Cycle Timing
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