SMJ320C80 Datasheet, PDF (24/157 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
floating-point status (FPST) register (0x0008)
FPST contains status and control information for the floating-point unit (FPU) as shown in Figure 13. Bits 17–21
are read/write FPU control bits. Bits 22–26 are read/write accumulated status bits. All other bits show the status
of the last FPU instruction to complete and are read only.
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
43210
dest
ai
a
z
a
o
a
u
a
x
s
m
f
s
v
m
drm
opcode
ee
10
pd
rm
mo i z o u x
dest
ai
az
ao
au
ax
sm
fs
vm
drm
opcode
e1
Destination register value
Accumulated value invalid
Accumulated divide-by-zero
Accumulated overflow
Accumulated underflow
Accumulated inexact
Sequential mode select
Floating-point stall
Vector fast mode
Rounding mode
00 – nearest
10 – positive ∞
01 – zero
11 – negative ∞
Last opcode
The tenth MSB of exponent
e0 The ninth MSB of exponent
pd Destination precision
00 – single float 10 – signed int
01 – double float 11 – unsigned int
rm Rounding mode
00 – nearest
10 – positive ∞
01 – zero
11 – negative ∞
mo Int multiply overflow
i Invalid
z Divide-by-zero
o Overflow
u Underflow
x Inexact
Figure 13. FPST Register
PP error (PPERROR) register (0x000A)
The bits in the PPERROR register reflect parallel processor errors (see Figure 14). The MP can use these when
a PP error interrupt occurs to determine the cause of the error.
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Reserved
h h h h Reserved i i i i Reserved f f f f
PP# 3 2 1 0
PP# 3 2 1 0
PP# 3 2 1 0
h PPhalted
I PP illegal instruction
f PP fault type
0 icache
1 Direct external access (DEA)
Figure 14. PPERROR Register
24
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443