82443MX Datasheet, PDF (99/173 Pages) Intel Corporation – PCIset

82443MX PCIset
after the starting address of the delayed transaction. A locked CPU cycle queued while data is being acquired
for the pending delayed transaction also results in data discard.
7.5.3 SOUTH BRIDGE/CLUSTER FUNCTIONALITY
The PCI logic in the South Bridge/Cluster serves as the PCI interface for cycles to and from DMA, RTC,
Interrupt Controllers, SMBus, GPIOs, Power Management logic, USB, IDE and X-bus.
7.5.3.1 South Bridge/Cluster as a PCI Target
The South Bridge/Cluster accepts cycles on the PCI bus on behalf of DMA, RTC, Interrupt Controllers,
SMBus, GPIOs, Power management, USB, IDE, X-bus, and all South Bridge/Cluster configuration registers.
Note, however, that the North Bridge/Cluster is the initiator in many of the cycles directed to the South
Bridge/Cluster.
The South Bridge/Cluster does positive/subtractive decoding depending on the mode selected.
Table 55 lists all of the PCI cycles that the South Bridge/Cluster can accept as a target.
Table 55. PCI Commands Supported by the South Bridge/Cluster when Acting as a PCI Target
PCI Command
C/BE[3:0]#
Encoding
Notes
Interrupt
Acknowledge
0000
Interrupt Controller can receive these cycles
Special Cycle
0001
Halt, Shutdown, Stop Grant cycles
I/O Read/
I/O Write
0010/
0011
Many of the functions have I/O ranges that can be disabled
and/or relocated.
Reserved
0100
N/A
Reserved
0101
N/A
Memory Read/
Memory Write
0110/
0111
USB, X-bus can receive these cycles
Reserved
1000
N/A
Reserved
1001
N/A
Configuration Read/ 1010/
Configuration Write 1011
South Bridge/Cluster decodes Type 0 configuration cycles to
Bus #0, Device #7 for the South Bridge/Cluster internal PCI
devices.
Memory Read
Multiple
1100
Aliased to Memory Read
Dual Address Cycle 1101
N/A
Memory Read Line 1110
Aliased to Memory Read
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