82443MX Datasheet, PDF (28/173 Pages) Intel Corporation – PCIset

82443MX PCIset
AC_SDATA_ O
OUT
AC_SYNC
O
AC’97 Serial Data Out. Serial TDM data output
AC’97 Sync. 48 KHz fixed rate sample sync
Signal
IRQ(14)
SERIRQ /
GPIO(7)
Table 8. Interrupt Signal Description
Type
Description
I
Interrupt Request 14. This interrupt input is connected to the IDE drive.
I/OD Serial Interrupt Request. This pin conveys the serial interrupt protocol. This
signal is muxed with GPIO(7).
Signal
RTCX1
RTCX2
Table 9. RTC Signal Description
Type
Description
Specia 32 KHz crystal. Connected to the 32.768 KHz crystal. If no external crystal is
l
used, then RTCX1 can be driven with the desired clock rate.
Specia 32 KHz crystal. Connected to the 32.768 KHz crystal. If no external crystal is
l
used, then RTCX2 should remain floating.
Signal
CLK48
DCLK
DCLKO
HCLKIN
OSC
PCICLK
Table 10. Clocks, Reset, PLLs and Miscellaneous Signal Description
Type
Description
I
48 MHz Clock. This signal runs the USB controller.
I
SDRAM Clock. Feedback reference from the external zero-delay SDRAM clock
buffer. The 440MX uses this clock when accessing an SDRAM array.
O
SDRAM Clock Out. 66 MHz SDRAM clock reference generated internally by the
440MX onboard PLL. It feeds an external buffer that produces multiple copies for
the DIMMs.
I
Host Clock In. This pin receives a buffered host clock. This clock is used by all
of the 440MX’s logic that resides is in the Host clock domain.
This clock is used by an internal PLL to generate clock references for 66 MHz
operations.
During POS/STR HCLKIN must be low.
This is the same or identical clock that goes to processor.
I
Oscillator Clock. Used for 8254 timers. Runs at 14.31818 MHz.
I
PCI Clock. This is a buffered PCI clock reference that is synchronously derived
by an external clock synthesizer component from the host clock. This clock is
used by all of the 440MX’s logic that resides in the PCI clock domain.
During POS/STR PCLKIN must be low.
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