82443MX Datasheet, PDF (33/173 Pages) Intel Corporation – PCIset

Signal
GPIO(26)
MCCS# /
GPIO(25)
MEMR#
MEMW#
PCS(1)# /
GPIO(16)
PCS(0)# /
GPIO(19)
RSTDRV
SA[18:0]
82443MX PCIset
Type
Description
to KBC. This signal is muxed with GPIO(26).
O / I/O Microcontroller Chip Select. Dedicated chip select for an external
microcontroller. The I/O registers for the microcontroller are hard coded to I/O
locations 62h and 66h.
During Reset:
After Reset:
During POS:
High
High
High
This signal is muxed with GPIO(25).
I/O
Memory Read. MEMR# is the command to a memory slave that it may drive
data onto the X-bus data bus.
During Reset:
After Reset:
During POS:
High-Z
High
High
I/O
Memory Write. MEMW# is the command to a memory slave that it may latch
data from the X-bus data bus.
During Reset:
After Reset:
During POS:
High-Z
High
High
O / I/O
Programmable Chip Selects. This active low chip select is asserted for ISA I/O
cycles that hit the range programmed into the Device Monitors[9,10] Function 3,
PM I/O space. It is assumed that the peripheral selected via this pin resides on
the X-bus.
NOTE: PCS(1:0)# pins are included in the GPIO section (Section 4.1.2).
O
Reset Drive. The 440MX asserts RSTDRV to reset devices that reside on the X-
bus. The 440MX asserts this signal during a hard Reset and during power-up.
RSTDRV is asserted during power-up and de-asserted after PWROK is driven
active. RSTDRV is also driven active for a minimum of 1 ms if a hard Reset has
been programmed in the RC Register.
During Reset:
After Reset:
During POS:
High
Low
Low
I/O
System Address Bus. These address lines define the selection with the
granularity of one byte within the 512KB section of memory. For I/O accesses,
only SA(15:0) are used. The 440MX always owns the X-bus during slave and
legacy DMA cycles. SA[18:0] are at an unknown state upon PCIRST#.
DURING A DMA I/O CYCLE, THE ADDRESS BUS WILL BE DRIVEN TO 00H
TO PREVENT OTHER I/O DEVICES FROM FALSELY DECODING THE
CYCLE.
During Reset:
After Reset:
During POS:
High-Z
Undefined
Last Address
21