82443MX Datasheet, PDF (139/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.10.1.6 Interrupt Masks
7.10.1.6.1 MASKING ON AN INDIVIDUAL INTERRUPT REQUEST BASIS
Each interrupt request input can be masked individually by the Interrupt Mask Register (IMR). This register is
programmed through OCW1. Each bit in the IMR masks one interrupt channel, if it is set to a 1. Bit 0 masks
IRQ0, Bit 1 masks IRQ1, and so forth. Masking an IRQ channel does not affect the other channel's operation,
with one exception: Masking IRQ2 on CNTRL-1 masks off all requests for service from CNTRL-2. The
CNTRL-2 INTR output is physically connected to the CNTRL-1 IRQ2 input.
7.10.1.6.2 SPECIAL MASK MODE
Some applications may require an interrupt service routine to dynamically alter the system priority structure
during its execution under software control. For example, the routine may wish to inhibit lower priority requests
for a portion of its execution but enable some of them for another portion.
The difficulty is that if an Interrupt Request is acknowledged and an End of Interrupt command did not reset its
IS bit (i.e., while executing a service routine), the Interrupt Controller would have inhibited all lower priority
requests with no easy way for the routine to enable them.
The Special Mask mode enables all interrupts not masked by a bit set in the Mask Register. Interrupt service
routines that require dynamic alteration of interrupt priorities can take advantage of the Special Mask mode.
For example, a service routine can inhibit lower priority requests during a part of the interrupt service, then
enable some of them during another part.
In the Special Mask mode, when a mask bit is set to 1 in OCW1, it inhibits further interrupts at that level and
enables interrupts from all other levels (lower as well as higher) that are not masked.
Thus, any interrupts may be selectively enabled by loading the Mask Register with the appropriate pattern.
Without Special Mask mode, if an interrupt service routine acknowledges an interrupt without issuing an EOI
to clear the IS bit, the interrupt controller inhibits all lower priority requests. The Special Mask mode provides
an easy way for the interrupt service routine to selectively enable only the interrupts needed by loading the
Mask Register.
Special Mask mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.
7.10.1.7 Reading the Interrupt Controller Status
The input status of several internal registers can be read to update the user information on the system. The
Interrupt Request Register (IRR) and In-Service Register (ISR) can be read via OCW3. The Interrupt Mask
Register (IMR) is read via a read of OCW1. This section briefly describes IRR, ISR, and IMR.

Interrupt Request Register (IRR): This 8-bit register that contains the status of each interrupt request
line. Bits that are clear indicate interrupts that have not requested service. The Interrupt Controller clears
the IRR's highest priority bit during an interrupt acknowledge cycle. (Not affected by IMR).

In-Service Register (ISR): This 8-bit register indicates the priority levels currently receiving service. Bits
that are set indicate interrupts that have been acknowledged and their interrupt service routine started.
Bits that are cleared indicate interrupt requests that have not been acknowledged, or interrupt request
lines that have not been asserted. Only the highest priority interrupt service routine executes at any time.
The lower priority interrupt services are suspended while higher priority interrupts are serviced. The ISR
is updated when an End of Interrupt Command is issued.
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