82443MX Datasheet, PDF (75/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Byte
17
36-41
42
Function
# Banks on each SDRAM Device
Access time from clock for CAS# latency 1 through 7
Data width of SDRAM components
These bytes collectively provide enough data to program the DRAM registers. For example, to program the
DRB (DRAM Row Boundary) Registers, the size of each row must be determined. The number of row
addresses (byte 3) plus the number of column addresses (byte 4) plus the number of banks on each SDRAM
device (byte 17) collectively determines the total address depth of a particular row of SDRAM. Since a row is
always 64 data bits wide, the size of the row is easily determined for programming the DRB Registers.
Once the type of DRAM has been detected, this information must then be programmed into the DRAM Row
Boundary Registers. The 440MX uses the DRAM Row Type information in conjunction with the DRAM
timings set in the DRAM Timing Register to optimally configure DRAM accesses.
7.2.3 SDRAM CYCLE ENCODING
Table 42 through Table 44 show the SDRAM cycle encoding using CS#, SRAS#, SCAS#, WE# and bank
select.
Table 42. Command Truth Table
Function
Symbol CKE CKE CS# SRAS# SCAS# WE# A11
n-1 n
Device deselect
DSEL
HX H
X
X
X
X
No Operation
NOP
HX L
H
H
H
X
Read
READ
HX L
H
L
H
V
Read w/ auto precharge
READAP H X L
H
L
H
V
Write
WRIT
HX L
H
L
L
V
Write w/ auto precharge
WRITEAP H X L
H
L
L
V
Bank Activate
ACT
HX L
L
H
H
V
Precharge select bank
PRE
HX L
L
H
L
V
Precharge all banks
PALL
HX L
L
H
L
X
Auto refresh
CBR
HH L
L
L
H
X
Self refresh entry from IDLE SLFRSH H L L
L
L
H
X
Self refresh exit
SLFRSHX L H H
X
X
X
X
Power Down entry from
PWRDN H L X
X
IDLE
X
X
X
Power Down exit
PWRDNX L H X
X
X
X
X
A10 A9-A0
X
X
X
X
L
V
H
V
L
V
H
V
V
V
L
X
H
X
X
X
X
X
X
X
X
X
X
X
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