82443MX Datasheet, PDF (58/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Cycles other than those intended to be converted to PCI configuration cycles are sent to the internal PCI bus,
broadcast as I/O cycles to the external PCI bus, and positively or subtractively decoded by the 440MX South
Bridge/Cluster for I/O regions residing in or behind the 440MX South Bridge/Cluster.
The processor allows 64K+3 bytes of I/O addressable space to be addressed. Processor I/O addresses are
propagated without any translation onto the destination bus except for I/O to I/O-to-configuration space
conversions. This provides addressability for 64K+3 byte locations. Note that the upper 3 three locations can
be accessed only during I/O address wrap-around when the processor bus A16# address signal is asserted.
A16# is asserted on the processor bus whenever an I/O access is made to the 4four- byte range starting from
address 0FFFDh, 0FFFEh, or 0FFFFh. A16# is also asserted when an I/O access is made to the 2two- byte
range starting from address 0FFFFh.
I/O write cycles are not posted.
The I/O map is divided into fixed and variable ranges. Fixed ranges cannot be moved, but in some cases can
be disabled. Variable ranges can be moved and can also be disabled.
6.6.1 FIXED I/O ADDRESS RANGES
Table 34 shows the Fixed I/O decode ranges positively decoded by the 440MX South Bridge/Cluster. If a PCI
master targets fixed I/O ranges, they are positively decoded at Medium speed.
Address ranges that are not listed or are marked Reserved are NOT positively decoded (unless assigned to
one of the variable ranges) but may be subtractively decoded if subtractive decode mode is enabled.
I/O
Alias
Address
000h
001h
002h
003h
004h
005h
006h
007h
008h
008h
009h
00Ah
010h
011h
012h
013h
014h
015h
016h
017h
018h
018h
019h
01Ah
00Bh
01Bh
Table 34. Fixed I/O Ranges Decoded by the 440MX
Register Name/Function
Bus
Master
Access
Forwarded
to ISA/EIO?
Default
Value
Reg.
Type
DMA Base/Current Address (Ch0) CPU / PCI Never
XXXXh R/W
DMA Base/Current Byte/Word (Ch0) CPU / PCI Never
XXXXh R/W
DMA Base/Current Address (Ch1) CPU / PCI Never
XXXXh R/W
DMA Base/Current Byte/Word (Ch1) CPU / PCI Never
XXXXh R/W
DMA Base/Current Address (Ch2) CPU / PCI Never
XXXXh R/W
DMA Base/Current Byte/Word (Ch2) CPU / PCI Never
XXXXh R/W
DMA Base/Current Address (Ch3) CPU / PCI Never
XXXXh R/W
DMA Base/Current Byte/Word (Ch3) CPU / PCI Never
XXXXh R/W
DMA Command Register (Ch 0-3) CPU / PCI Never
00h
WO
DMA Status Register (Ch 0-3)
CPU / PCI Never
00h
RO
DMA Request Register (Ch 0-3)
CPU / PCI Never
000000XX WO
Mask Register - Write Single Mask CPU / PCI Never
(Ch 0-3)
000001XX WO
DMA Channel Mode Register (Ch 0-3) CPU / PCI Never
000000XX WO
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