82443MX Datasheet, PDF (92/173 Pages) Intel Corporation – PCIset

82443MX PCIset
AC_SYNC
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48 KHz fixed rate sample sync
7.4.4 SYSTEM INITIALIZATION
The AC'97 circuitry is reset on power up by combining the PCIRST# signal with the AC'97 AC_RST# signal.
The AC_RST# signal remains asserted (low) until the driver writes the cold reset bit in the Global Control
Register to 1 (either the audio or the modem driver can do this, because setting this bit in any one register will
suffice since they both reflect the same register). During operation, the system can be reset by clearing the
AC'97 AC_RST# bit in the Global Control/Status Register (NABMBAR + 60h). After Reset, a read to Mixer
Register 00h indicates what type of hardware resides in the codec. If the codec is not present, i.e., AC'97 is
not supported, codec ready is never seen by the controller.
7.4.5 CLOCKING
The AC’97 codec derives its clock internally from an externally attached 24.576 MHz crystal1, and drives a
buffered and divided down (1/2) clock to its digital companion controller over AC-link under the signal name
“BIT_CLK”. Clock jitter at the DACs and ADCs is a fundamental impediment to high quality output, and the
internally generated clock provides AC’97 with a clean clock that is independent of the physical proximity of
AC’97’s companion digital controller (henceforth referred to as the “AC’97 controller”). The secondary codec is
clocked by the BIT_CLK supplied by the primary codec.
The beginning of all audio sample packets, or “Audio Frames”, transferred over AC-link is synchronized to the
rising edge of the “SYNC” signal. SYNC is driven by the AC’97 controller. The AC’97 controller takes
BIT_CLK as an input and generates SYNC by dividing BIT_CLK by 256 and applying some conditioning to
tailor its duty cycle. This yields a 48 KHz SYNC signal whose period defines an audio frame. Data is
transitioned on AC-link on every rising edge of BIT_CLK, and subsequently sampled on the receiving side of
AC-link on each immediately following falling edge of BIT_CLK.
7.4.6 DIGITAL INTERFACE
7.4.6.1 Multi-Point ACLink
The multi-point ACLink method allows up to two codecs on the link. By definition there is a Primary and a
Secondary codec. The two devices have completely orthogonal register sets, i.e., they do not share registers
and each is individually accessible. Both devices share SDATA_OUT from the controller, but each has its
own SDATA_IN pin back to the controller. This prevents contention of the two devices on one input. It also
keeps any unnecessary complexity from the codecs.
7.4.6.1.1 PRIMARY CODEC
The Primary device is completely backwards compatible with existing AC’97 solutions. It generates the
master BIT_CLK for both the controller and the secondary codec. Its registers are located in the same place
as defined in AC’97. The primary codec can only be an AC’97, AC’97 Rev 2.0 or an AMC’97.
1 _{A 24.576 MHz crystal is recommended, but an external oscillator may also be input to AC ’97 XTAL_IN.}
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