82443MX Datasheet, PDF (113/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Byte
Word
Table 62. PCI Data Bus vs. DMA I/O Port Size
PCI DMA I/O Port Size
PCI Data Bus Connection
AD[7:0]
AD[15:0]
Table 63. DMA I/O Cycle Width vs. BE[3:0]#
BE[3:0]#
DMA I/O Cycle Width
1110b
8 bits
1100b
16 bits
Note:
For verify cycles, the value of the Byte Enables (BE#s) is a “don’t care.”
Every DMA device (including Secondary Bus Arbiters) must recognize a valid signal on its GNT# combined
with the DMA I/O address as its command authorization to initiate a DMA access cycle. the 440MX is required
to assert the DMA I/O device’s GNT# signal until the data phase of the I/O portion of the DMA transfer.
7.7.4 DSTRIBUTED DMA
7.7.4.1 Overview
The Distributed DMA scheme is based on the concept that the registers associated with individual DMA can
physically reside outside of the 440MX, specifically on other PCI devices. The Distributed DMA logic in the
440MX is only used when the CPU performs accesses to the 8237 registers — data movement is the
responsibility of the peripheral.
Separate algorithms are followed depending whether the CPU attempts a read cycle or write cycle. Each is
covered separately. The 440MX is able to determine if a particular DMA channel is "distributed" based on the
PCI configuration space.
7.7.4.2 Additional Configuration
The 440MX contains two registers to indicate the I/O locations for the relocated DMA registers for the DDMA
peripherals. The first register indicates the offset of the registers associated with DMA channels 0-3. The
second indicates the offset of the registers associated with DMA Channels 5-7. Channel 4 is assumed to be
unavailable, The pointers require that the registers for Channels 0 and 5 start on a 64-byte boundary.
Channels 1 and 6 appear 16 bytes above 0 and 5. Channels 2 and 7 appear 32 bytes above Channels 0 and
5. Channel 3 appears 48 bytes above Channel 0.
The BIOS or other configuration software is responsible for programming the DDMA peripherals to the
corresponding locations.
During ALT ACCESS mode, the write-only registers become readable, and the read-only registers become
writeable. This allows a mobile BIOS to save and restore the state of the DMA controller for proper
resumption from SUSPEND. It is assumed that during ALT ACCESS mode read and write cycles, the DDMA
logic is not used.
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