82443MX Datasheet, PDF (80/173 Pages) Intel Corporation – PCIset

82443MX PCIset
1. If both banks are idle and CKE is inactive (low level), then in power down mode.
2. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
3. If both banks are idle and CKE is inactive (low level), then in Self refresh mode.
4. Illegal if trcd is not satisfied.
5. Illegal if tras is not satisfied.
6. Must satisfy burst interrupt condition.
7. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
8. Must mask preceding data that does not satisfy tdpl.
9. Illegal if trrd is not satisfied.
10. Illegal for a single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.
7.2.4 DRAM ADDRESS TRANSLATION AND DECODING
The 440MX address decoders translate the address received on the host bus or PCI bus to an effective
memory address. Translation supports 16- and 64-Mbit DRAM devices with 2 KB, 4 KB and 8 KB page sizes.
Page size varies per row depending on how many column address lines are used for a given row. Rows
containing SDRAMs with 8 column lines have a 2 KB page size. Those with 9 column lines have a 4 KB page
size and those with 10 column address lines have an 8 KB page size. The multiplexed row/column address to
the DRAM memory array is provided by the MA[13,12#,11#,10,(9:0)#] signals. The MA[13,12#,11#,10,(9:0)#]
bits are derived from the host address bus as defined by Table 45.
Row and Column address muxing on the MA[13,12#,11#,10,(9:0)#] lines is determined on a row-by-row basis
allowing for three possible page sizes. SDRAMs have 8, 9 or 10 column lines allowing for 2 KB, 4 KB or 8 KB
page sizes. The page size is determined primarily by the row size. When implemented with 2Mx32 devices,
four banks are supported for that row. That is, up to four pages may be opened within that row. Since the 64-
Mb 2Mx32 devices have only eight column address lines, rows using these devices have only a 2 KB page
size while those implemented with the 16-Mb 2Mx8 have nine column address lines yielding a 4 KB page size.
The 16-bit Page Size Register is used to distinguish between page sizes for a 32-MB SDRAM row. It contains
a bit per row to specify the page size for that row. When a bit is set to 1, the 440MX uses the larger of the two
possible page sizes. Table 45 shows the address muxing requirements for each of the supported row sizes.
Row size is internally computed using the values programmed in the DRB Registers. Page size is determined
by the row size and the Page Size Register. Note that the column address for the 32 M, 64 M and 128 M row
sizes has P for MA10. P is sent out on MA10.
Either two or four pages can be open at any time within any row. If a row contains SDRAMs based on 16-Mb
technology (i.e., 12x8/9/10 devices), then two pages can be open at a time within that row. If a row contains
SDRAMs based on 64-Mb technology, (i.e., 14x8/9/10 devices) then four pages can be open at a time within
that row.
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