82443MX Datasheet, PDF (25/173 Pages) Intel Corporation – PCIset

Signal
Signal
SPKR /
GPIO(14)
TEST#
Signal
AD[31:0]
C/BE[3:0]#
CLKRUN#
82443MX PCIset
Type
Description
Disk DMA Ready (Ultra33 DMA Writes to Disk). When writing to disk, this signal
is de-asserted by the disk to pause burst data transfers.
Table 5. Other System/Test Signal Description
Type
Description
O / I/O
Speaker. The SPKR signal is the output of counter 2 and is internally "ANDed"
with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external
speaker driver device. Upon PCIRST#, its output state is 0. This signal is muxed
with GPIO(14). Refer to Section 4.2 for the pin count.
I
Intel Reserved signal. This signal must be strapped to an external pull-up resistor.
Table 6. PCI I/F Signal Description
Type
Description
I/O
PCI Address/Data. AD[31:0] is a multiplexed address and data bus. During the
first clock of a transaction, AD[31:0] contain a physical byte address (32 bits).
During subsequent clocks, AD[31:0] contain data.
I/O
Bus Command and Byte Enables. The command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used
as Byte Enables.
C/BE[3:0]# Command Type
0000
0001
0010
0011
0110
0111
1010
1011
1100
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
All command encodings not shown here are Reserved. The 440MX does not use
reserved values, and does not respond if a PCI master generates a cycle using
one of the reserved values.
I/OD PCI Clock Run. CLKRUN# uses a protocol between the 440MX and various
peripherals for dynamic starting and stopping of the PCI clock.
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