82443MX Datasheet, PDF (23/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Table 3. Memory I/F Signal Description
Signal
Type
Description
CKE(3:0)#
O
Clock Enable (SDRAM). Clock Enable is used to signal a self-refresh or power-
down command to an SDRAM array when entering system Suspend. CKE is also
used to dynamically power down inactive SDRAM rows.
CS(3:0)#
O
Chip Select (SDRAM). For memory rows configured with SDRAM these pins
select the particular SDRAM components during the active state.
DQM(7:0)
O
Input/Output Data Mask (SDRAM). These pins act as synchronized output
enables during read cycles and as a byte enables during write cycles. The read
cycles require Tdqz clock latency before the functions are performed. In the case
of write cycles, byte-masking functions are performed during the same clock
when write data is driven (i.e., 0 clock latency).
MA(13,12#,11# O
,
10, (9:0)#)
Memory Address (SDRAM). MA(13,12#:11#,10,(9:0)#) signals provide the
multiplexed row and column address to DRAM. Each Memory address line has a
programmable buffer strength to optimize for different signal loading conditions.
MD(63:0)
I/O
Memory Data (SDRAM). These signals interface to the DRAM data bus.
SCAS#
O
SDRAM Column Address Strobe (SDRAM). The SCAS# signal generates
SDRAM commands encoded on SRAS#/SCAS#/WE# signals.
SRAS#
O
SDRAM Row Address Strobe (SDRAM). The SRAS# signal generates SDRAM
commands encoded on SRAS#/SCAS#/WE# signals.
WE#
O
Write Enable Signal (SDRAM). WE# is asserted during writes to DRAM. The
WE# lines have a programmable buffer strength that can be optimized for
different signal loading conditions.
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