82443MX Datasheet, PDF (39/173 Pages) Intel Corporation – PCIset

82443MX PCIset
4.4 Power-Up State Initial Value
The signal states immediately after Reset (PCIRST#) and during POS/STR (Power-on Suspend and
Suspend-to-RAM states) are defined using the following headings:
RE
State during Reset
SR
State immediately following Reset (PCIRST#)
SP
State during POS/STR
ISO
Signal is isolated during POS/STR
The signal states are defined using the following nomenclature:
Z
Three-stated
L
Driven low
H
Driven High
DR
Driven to active logic state
U
Undefined
4.5 Power-On Reset Pin Values
Table 24 lists the input/output pin values before and after Reset, POS, STR, STD and Mechanical Off. The
pu/pd column indicates whether an internal or an external pull-up or pull-down resistor is required. Internal
pull-up/pull-down resistors are used to set default strapping values. The internal resistors are disabled after
PCIRST# goes inactive.
Table 24. Power-On Reset Values by Signal Group
Signal
Group
Signal
Host
A20GATE
Interface A20M#
Signals(1)
ADS# ⁽⁴⁾
BNR# ⁽⁴⁾
BPRI# ⁽⁴⁾
BREQ0# ⁽⁶⁾
CPURST# ⁽²⁾
DBSY# ⁽⁴⁾
Power Buffer External During After
Plane Type Pu/Pd Reset Reset
During
POS
During
STR
During
STD
Mech.
OFF
Main 3.3/5V No
Input Input
Input
Hi-Z
Pwrdn Pwrdn
Main OD Pu
Note(7) Hi-Z
Last or Hi-Z
A20GATE
Pwrdn Pwrdn
Main GTL+
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pwrdn Pwrdn
Main GTL+
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pwrdn Pwrdn
Main GTL+
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pwrdn Pwrdn
Main GTL+
Hi-Z/Low Hi-Z/Low Hi-Z
Hi-Z
Pwrdn Pwrdn
Main GTL+ Pd
Low
Hi-Z
Hi-Z
Hi-Z
Pwrdn Pwrdn
Main GTL+
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pwrdn Pwrdn
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