82443MX Datasheet, PDF (71/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.2 Memory Interface
7.2.1 DRAM INTERFACE
7.2.1.1 DRAM Interface Overview
The 440MX integrates a main memory DRAM controller that supports a 64-bit SDRAM array. The 440MX
generates the CS#, DQM, SCAS#, SRAS#, SCLK, WE#, CKE and multiplexed addresses,
MA[13,(12:11)#,10,(9:0)#] for the DRAM array. For CPU/PCI to DRAM cycles, the address and data flows
through the 440MX. The 440MX’s DRAM interface operates on a clock that is synchronous to the CPU’s FSB
clock at 66 MHz. The DRAM controller interface is fully configurable through a set of control registers.
The 440MX supports industry standard 64-bit wide SDRAM DIMM modules. The 14 multiplexed address
lines, MA[13:0], allow the 440MX to support 1M, 2M, 4M, 8M, and 16M x64 DIMMs. The 440MX has 4 CS#
lines enabling the support of up to four 64-bit rows of DRAM in two DIMM modules. For write operations of
less than a Qword in size, the 440MX performs a byte-wide write with DQMs. The 440MX targets 66 MHz
SDRAM and supports both single and double-sided DIMMs. The 440MX provides refresh functionality with
programmable rate (normal DRAM rate is 1 refresh/15.6 s). Additionally, the 440MX provides a seven-deep
refresh queue. The 440MX can be configured via the Paging Policy Register to keep multiple pages open
within the memory array. Pages can be kept open in all rows of memory. When 4-bank SDRAM devices
(64Mb technology) are used for a particular row, up to 4 pages can be kept open within that row. When using
2-bank SDRAM devices in a particular row, up to 2 pages can be kept open within that row.
The DRAM interface of the 440MX is configured by the SDRAM Control Register, the NBXCFG Register bits,
and the four DRAM Row Boundary (DRB) Registers. The four DRB Registers define the size of each row in
the memory array, enabling the 440MX to assert the proper CS# for accesses to the array.
7.2.2 DRAM ORGANIZATION AND CONFIGURATION
The 440MX supports 64-bit DRAM configurations. In the following discussion, the term row refers to a set of
memory devices that are simultaneously selected by one CS#. The 440MX supports a maximum of 4 rows of
SDRAM memory. A row may be composed of discrete DRAM devices, single-sided or double-sided DIMMs.
The DRAM interface consists of the following pins:

MA[13,(12:11)#,10,(9:0)#]

MD[63:0]

DQM[7:0]

SRAS#

SCAS#

WE#

CS[3:0]#

CKE[3:0]
One CS# line is provided for each row. The SRAS#, SCAS# and WE# drive up to 4 rows of SDRAM. Most
pins utilize programmable strength output buffers. When a row contains 16-Mb SDRAMs, MA11# functions
as a Bank Select line. When a row contains 64-Mb or 128-Mb SDRAMs, MA[12:11]# function as Bank
Addresses (BA[1:0], or Bank Selects).
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