82443MX Datasheet, PDF (14/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Features
440MX
I/O Components
Super I/O (FDC, PP, SP, IR), optional RTC
External (on X-bus only)
Interface support for KBC, Flash, and other slow
devices
X-bus (8-bit)
Power Management Functions
ACPI 1.0 compliant power management
Yes
Legacy Power Management support
Yes
System Management Support
SMBus
Yes
Wired For Management (WFM)
Yes
Miscellaneous
General Purpose Input/Output
31 GPIOs
Programmable Chip Selects
2 (muxed w/GPIO) for X-bus option
USB
2 ports / 1 HCI
1.2 440MX Features

Processor/Host bus support
 Optimized for mobile Celeron processors or Pentium II processors at 66 MHz host bus frequency
 Supports 32-bit mobile Celeron processor / Pentium II processor bus addressing (no support for
processor host bus 36-bit address extension)
 4 or 1 deep in-order queue; 4 or 1 deep request queue
 Supports uni-processor systems only
 In-order transaction and dynamic deferred transaction support
 GTL+ bus driver technology (gated GTL+ receivers for reduced power)

Integrated DRAM controller
 8 MB to 256 MB using 16/64/128 Mb generation
 Supports up to 2 double-sided DIMMs (4 rows memory)
 64-bit data interface without ECC
 66 MHz memory clock
 Standard and registered SDRAM (Synchronous) DRAM support (x-1-1-1 access)
 Command issue rate of one per clock
 Supports ONLY 3.3V DIMM DRAM configurations
 Support for 16-/64-/128- Mbit DRAM devices
 Support for symmetrical and asymmetrical DRAM addressing
 Support for x8, x16 and x32 DRAM device width
2