82443MX Datasheet, PDF (120/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Comment: Clear Mask Register
To facilitate peripheral implementation, the Distributed DMA specification does not have the peripherals
implement the Clear Mask command. Instead, a write to the Clear Mask Command Register (which has a
don't care data value) causes writes to all the distributed channels associated with that 8237.
Thus, when a write occurs to the Clear Mask Command Register, the 440MX performs up to four writes to the
Write All Masks Register (Base Pointer + channel # + Fh) with a data value of 0h.
7.7.4.5 Power Management Implications
When the system powers down and resumes, it may need to read and later restore values associated with the
DMA controller.
SYSTEM-LEVEL RESTRICTION:
Peripherals using the distributed DMA protocol with the 440MX must ensure all register values are
readable and restorable.
If the system software attempts to read a shared register, and one of the distributed channels is
powered down, then an SMI# must be generated to wake up the peripherals. After the read of the
register, another SMI# must be generated to again reduce the power.
NOTE:
SMI# is caused by the 440MX receiving a master abort (because the slave does not generate a
DEVSEL# within the required time). If the P4MA_EN bit (bit 4) in the GLBL_EN Register is set, then
the master abort causes the SMI#.
7.7.4.6 Other Clarifications
If another PCI master attempts to read or write to one of the DMA controller registers, that cycle is retried until
the PC DMA protocol completes. This prevents two outstanding requests.
If the 440MX should experience a PCI time-out when attempting to read or write to a peripheral (as part of the
distributed DMA protocol), then the normal target abort indicator goes active in the Device Status Register in
the PCI configuration space.
7.8 Timer
The Timer block integrates one 82C54 timer/counter.
7.8.1 COUNTER/TIMERS
The 440MX contains three counters that are equivalent to those found in the 82C54 programmable interval
timer (see Table 66). The three counters are contained in one timer unit, referred to as Timer-1. Each counter
output provides a key system function. Counter 0 is connected to interrupt controller IRQ0 and provides a
system timer interrupt for a time-of-day, diskette time-out, or other system timing functions. Counter 1
generates a refresh request signal and Counter 2 generates the tone for the speaker. The 14.31818 MHz
counters normally use OSC as a clock source.
Full details of this counter can be found in the 82C54 Data Sheet.
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