82443MX Datasheet, PDF (105/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.6.2.4.1 CHANNEL PRIORITY
For priority resolution the DMA consists of two logical channel groups: DMA-1 = Channels 0-3, and DMA-2 =
Channels 4-7 (see Figure 12 in Section 7.6.2). Each group may be in either fixed or rotate mode, as
determined by the DMA Command Register.
The source (DREQx) of the DMA request is transparent to the final priority resolution logic. A generic request
from the DMA is sent to the X-bus Arbiter. DMA I/O slaves normally assert their DREQ line to arbitrate for
DMA service. However, a software request for DMA service can be presented through each channel's DMA
Request Register. A software request is subject to the same prioritization as any hardware request. Please
see Section 7.6.2 for Request Register programming details.
7.6.2.4.1.1
Fixed Priority
The initial fixed priority structure is as follows:
High priority.....Low priority
(0, 1, 2, 3) 5, 6, 7
The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, Channel 0 has the highest priority, and
Channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume the priority position of Channel 4 in DMA-
2, thus taking priority over Channels 5, 6, and 7 (see Figure 13).
DMA System
(2-W ay
Rotation)
CH0 CH1 CH2 CH3 CH5 CH6 CH7
IBISAARB.drw
Figure 13. X-Bus Arbiter with DMA in Fixed Priority (2-way rotation)
7.6.2.4.1.2
Rotating Priority
Rotation allows for "fairness" in priority resolution. The priority chain rotates so that the last channel serviced
is assigned the lowest priority in the channel group (0-3, 5-7).
Channels 0-3 rotate as a group of four. They are always placed between Channel 5 and Channel 7 in the
priority list.
Channels 5-7 rotate as part of a group of four. That is, Channels 5-7 form the first three positions in the
rotation, while channel group (0-3) comprises the fourth position in the arbitration (see Figure 14).
Table 57 demonstrates rotation priority.
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