82443MX Datasheet, PDF (85/173 Pages) Intel Corporation – PCIset

82443MX PCIset
3. Enable the throttling functions by setting bit 2 of each of the corresponding registers. Bits 1:0 of these
registers must be “00” at all times. Note that the above throttling fields must be set to non-zero values
before the functions are enabled.
4. Set the TLOCK bit. Once TLOCK is set to a ‘1’, the Throttling Registers can be read but cannot be
modified. Once locked, throttling function attributes can be modified after the next cold reset.
5. As an option, SERR# generation may be enabled when throttling conditions are met, if the platform
needs to generate an interrupt for this case. SERR# generation is not protected by TLOCK.
7.2.8 SDRAM PERFORMANCE DESCRIPTION
The overall SDRAM performance is controlled by the DRAM Timing Register, the pipelining depth used in the
440MX, and the DRAM speed grade. In addition, exact system performance depends on the total memory
supported, external buffering and memory array layout. As frequencies increase, the flight times for DRAM
signals become important and contribute to the performance achieved.
7.2.9 SDRAM OPTIMIZATIONS
7.2.9.1 Dual and Quad Bank Support
The 440MX supports 16-Mb, 64-Mbit, and 128-Mbit SDRAM technology. When 16-Mb SDRAMs are used for
a particular row of memory, the 440MX uses 12x8/9/10 (row x column) addressing and can keep up to two
pages open within that row. When 64-Mb technology is used for a particular row of memory, the 440MX uses
14x8/9/10 or 13x8 (in the case of a row containing two 2Mx32 SDRAM devices) addressing and can keep up
to four pages open within that row provided the SDRAMs support four banks. Some 64-Mb SDRAMs may be
available with only a two-bank architecture. These parts are also supported by the 440MX. Note that when a
2Mx32 SDRAM device is used and the device is a two-bank implementation, the addressing for this part is the
same as for a 2Mx8 (16Mb) device, or 12x9. The banks per row bits (BPR) in the Paging Policy Register are
used to indicate two versus four-bank SDRAMs on a row-by-row basis. Each bit in the eight-bit BPR field
corresponds to one row of memory. When a bit is set to 0, it indicates that the corresponding row has only
two banks. When a bit is set to 1, it indicates that the corresponding row has four banks and thus can have
up to four pages open at any time. The banks per row information is obtained by the BIOS via the Serial
Presence Detection port on the SDRAM DIMMs and then programmed into the BPR field.
7.3 System Memory Management
7.3.1 SMRAM RANGE OVERVIEW
The 440MX supports the use of main memory as System Management RAM (SMRAM) enabling the use of
System Management Mode. The 440MX supports two SMRAM options: Compatible SMRAM (C_SMRAM)
and Extended SMRAM (E_SMRAM). SMRAM space provides a memory area that is available for the SMI
handler's and code and data storage. This memory resource is normally hidden from the system OS so that
the processor has immediate access to this memory space upon entry to SMM. The 440MX provides the
following three SMRAM options:

Below 1 Mbyte option that supports compatible SMI handlers.

Above 1 Mbyte option that allows new SMI handlers to execute with write-back cacheable SMRAM.
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