82443MX Datasheet, PDF (116/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Register
Algorithm
Temporary Address Since the 8237 does not permit read accesses to the Base Address Register, the
DDMA does not need to perform them.
For power-management purposes, the 440MX permits reading this register via the Alt
Access Mode.
Temporary Word
Count
Since the 8237 does not permit read accesses to the Base Address Register, the
DDMA does not need to perform them.
For power-management purposes, the 440MX permits reading this register via the Alt
Access Mode.
Status
The Status Register (one for each 8237) reports the TC status and DMA request
status for the four channels associated with each 8237.
For DMA Channels 0-3, the 8237 Status Register is mapped to ISA 0008h. The
440MX must perform up to four read cycles.
For DMA Channels 5-7, the 8237 Status Register is mapped to ISA 00D0h. The
440MX must perform up to three read cycles. Channel 4 is always assumed to be
inside the 440MX.
For read cycles, the 440MX assembles the Status Register as follows:
Bits 0 and 4 from Channel 0 (or Channel 4 if from the 2nd 8237)
Bits 1 and 5 from Channel 1 (or Channel 5 if from the 2nd 8237)
Bits 2 and 6 from Channel 2 (or Channel 6 if from the 2nd 8237)
Bits 3 and 7 from Channel 3 (or Channel 7 if from the 2nd 8237)
Command
The Command Register sets various configuration options.
For DMA Channels 0-3, the 8237 Command Register is mapped to ISA 0008h. The
440MX must perform up to four write cycles.
For DMA Channels 5-7, the 8237 Command Register is mapped to ISA 00D0h. The
440MX must perform up to three write cycles. Channel 4 is always assumed to be
inside the 440MX.
During write cycles, the 440MX copies the CPU's write value to all distributed
channels.
Temporary
The distributed DMA protocol does not support memory-to-memory transfers. The
distributed DMA logic should let this cycle pass to the 8237 and complete normally.
Mode
The Mode Register sets various configuration options. Because the low two bits of the
Mode Register are used to identify one of the four channels, only one PCI write cycle
is required.
For DMA Channels 0-3, the 8237 Mode Register is mapped to ISA 000Bh.
For DMA Channels 5-7, the 8237 Mode Register is mapped to ISA 00D6h. Channel 4
is always assumed to be inside the 440MX.
During write cycles, the 440MX copies the CPU's write value to the distributed
channel.
Single Channel
The Single Channel Mask Register sets or resets the mask of a single channel.
Because the low two bits of the Mode Register are used to identify one of the four
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