82443MX Datasheet, PDF (82/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Table 46. Programmable SDRAM Timing Parameters
Parameter
SDRAMC Bit
Values (SCLKs)
CAS# Latency
CL
2,3
RAS#-to-CAS# Delay
SRCD
2,3
RAS# Precharge
SRP
2,3
Leadoff CS# Assertion
LCT
3,4
The SDRAM timing parameters are controlled via the SDRAMC Register. To support different device speed
grades at 66 MHz, CAS# Latency, RAS#-to-CAS# Delay and RAS# Precharge are all programmable as either
two or three SCLKs. To provide flexibility, each parameter is controlled by a separate register bit; i.e., any
combination of CAS# Latency, RAS#-to-CAS# Delay and RAS# Precharge can be supported. One additional
bit, the Leadoff Timing bit, controls CS# assertion when the command lines (SRAS#, SCAS# and WE#) are
considered valid on the interface, and hence when CS# can be asserted for CPU read leadoff cycles. In the
fastest timing mode, CS# can be asserted in clock three. This enables a seven-clock page hit performance
with CAS# Latency, two devices and one clock MD-to-HD delay. This field controls when the first assertion of
CS# occurs for CPU-initiated read cycles. The assertion may be for a read, row activate or precharge
command. The MA lines along with the command lines (SRAS#, SCAS# and WE#) are driven in clock two,
however the clock-to-output delay timing is slower than in the other modes. Use of this mode may require a
lightly loaded SDRAM interface.
7.2.6 SDRAM PAGING POLICY
7.2.6.1 Overview
Open Page Arbitration (OPA) is a paging policy that leaves pages open when handing off DRAM ownership
among masters, and places no restrictions on the number of rows which may have open pages at any given
time.
OPA features include:

Pipelined arbitration allows row/bank/page operations for the next cycle to occur during a current DRAM
access.

Maintains two or four open banks, in up to eight rows at a time.
7.2.6.2 Open Page Arbitration Policies
At any given time, pages may be open in any of the eight rows of SDRAM memory. For each row, pages can
be open simultaneously in each bank, i.e., two banks/row for 16-Mbit SDRAM and (typically) four banks/row
for 64-Mbit SDRAM.
Open Page Arbitration is always enabled.
7.2.6.3 Selective Auto Precharge Policy
The Selective Auto Precharge (SAP) policy causes the 443BX DRAM controller to use Auto Precharge when
issuing commands on behalf of certain cycles.
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