82443MX Datasheet, PDF (54/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Memory Range
(Addresses in Hex)
000E0000 - 000EFFFF
Attributes
Target
WE/RE ROM BIOS
000F0000 - 000FFFFF WE/RE ROM BIOS
00100000 - TOM
(Top of Memory)
None
(TOM + 1) - FEBFFFFF None
FEC00000 - FECFFFFF None
Main memory
External PCI memory
Reserved
FED00000 - FFBFFFFF WE/RE
FFC00000 - FFFEFFFF WE/RE
External PCI memory
ROM BIOS or PCI memory
FFFF0000 - FFFFFFFF WE/RE ROM BIOS
Dependency/Comments
WE/RE attributes in PAM
Registers control whether this
range is directed to Main
Memory (only), or gets
forwarded to ROM BIOS.
WE/RE attributes in PAM
Registers control whether this
range is directed to Main
Memory (only), or gets
forwarded to ROM BIOS.
TOM is set by TOM Registers,
and is a maximum of 256 MB.
In other systems, this range
may be used for I/O APICs.
Destination based on enable
bits in ROM BIOS Decode
Enable Register at offset E3h,
device 7, function 0.
Enable for this range in ROM
BIOS Decode Enable Register
at offset E3h, device 7, function
0 is hardwired to 1. This range
is always targeted to ROM
BIOS.
6.2.1 COMPATIBILITY AREA
Table 33 shows how the compatibility memory area from 0-1 MB (0000 0000h - 0010 0000h) is divided into
address regions.
Table 33. Compatibility Memory Area
Address Range
Memory Area
0 - 512 KB
DOS Area
512 - 640 KB
DOS Area / Optional Fixed Memory Hole
640 - 768 KB
Video Buffer Area
768 - 896 KB in 16KB sections (total of 8 sections) Expansion Area
896 - 960 KB in 16KB sections (total of 4 sections) Extended System BIOS Area
42