82443MX Datasheet, PDF (42/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Signal
Group
Signal
Power Buffer External During After
Plane Type Pu/Pd Reset Reset
During
POS
During
STR
During
STD
Mech.
OFF
AC_SDATA_ Main 3.3V None Low
Low
Low
Hi-Z
Pwrdn Pwrdn
OUT
AC_SYNC
Main 3.3V None Low
Low
Low
Low
Pwrdn Pwrdn
Interrupt SERIRQ/
Signal GPIO[7]
Main 3.3/5V Pu
GPIO GPIO
Hi-Z/
Hi-Z
State State
GPIO
State
Pwrdn Pwrdn
RTC
RTCX[2:1]
Signals
RTC 3.3V No
Special Special Special Special Special Special
Clocks/ CLK48
Reset/
Main 3.3/5V No
Input Input
Input
ISO
Pwrdn Pwrdn
PLL/ Misc. OSC
Main 3.3/5V No
Input Input
Input
ISO
Pwrdn Pwrdn
Signals PCICLK
Main 3.3/5V No
Running Running Low
Low
Pwrdn Pwrdn
USB
USBPRT0[+:-] USB/ 3.3V Pd
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pwrdn
Signals
Resume
USBPRT1[+:-] USB/ 3.3V Pd
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pwrdn
Resume
OC[1:0]#
Resume 3.3V Pu
Input Input
Input
Input
Input
Pwrdn
SMBus SMBCLK
Resume 3.3V Pu
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pwrdn
Signals SMBDATA
Resume 3.3V Pu
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pwrdn
Power
Mgmt
Signals
BATLOW# /
GPIO[11]
Resume 3.3V _No(10) Input
Input
Input/
GPIO
State
Input/
GPIO
State
Input /
GPIO
State
Pwrdn
CPUSTP#
Main 3.3/5V No
High High
Low
ISO
Pwrdn Pwrdn
EXSMI#/
GPIO[24]
Resume 3.3V _No(10) Input Input
Input/
GPIO
State
Input/
GPIO
State
Input/
GPIO
State
Pwrdn
LID /
GPIO[10]
Resume 3.3V _No(10) Input Input
Input/
GPIO
State
Input/
GPIO
State
Input/
GPIO
State
Pwrdn
PCISTP#
Main 3.3/5V No
High High
Low
ISO
Pwrdn Pwrdn
PWRBTN#
Resume 3.3V No
Input Input
Input
Input
Input
Pwrdn
PWROK
RTC 3.3V No
Input Input
Input
Input
Input
Input
RI# /
GPIO[12]
Resume 3.3V _No(10) Input Input
Input/
GPIO
State
Input/
GPIO
State
Input/
GPIO
State
Pwrdn
RSMRST#
RTC 3.3V No
Input Input
Input
Input
Input
Input
SUS_STAT# Resume 3.3V No
Low
High
Low
Low
Low
Pwrdn
SUSA#
Resume 3.3V No
High High
Low
Low
Low
Pwrdn
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