82443MX Datasheet, PDF (97/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Table 54. PCI Commands Supported by North Bridge/Cluster when Acting as a PCI Initiator
440MX North Bridge/Cluster
Source Bus Command
Other Encoded
Information
Corresponding PCI
Command
C/BE[3:0]#
Encoding
Deferred Reply
Don’t Care
None
N/A
Interrupt Acknowledge Length  8 Bytes
Interrupt Acknowledge 0000
(BE[3:0]# = 1110)
Special Cycle
Shutdown
Special Cycle
0001
(AD[15:0] = 0000h)
Halt
Special Cycle
0001
(AD[15:0] = 0001h)
Stop Grant
Special Cycle
0001
(AD[15:0] = 0002h,
AD[31:16] = 0012h)
All other combinations None
N/A
Branch Trace Message None
None
N/A
I/O Read
Length  8 Bytes up to 4 I/O Read
byte enables asserted
0010
I/O Write
Length  8 Bytes up to 4 I/O Write
byte enables asserted
0011
Length < 8 Bytes without Memory Read
all BEs asserted
0110
Memory Read
(Code or Data) or
Length = 8 Bytes with all Memory Read
BEs asserted
1110
Memory Read Invalidate Length = 16 Bytes
None
N/A
Length = 32 Bytes
Code Only
Memory Read
1110
Memory Write
Length < 8 Bytes without Memory Write
all BEs asserted
0111
Length = 16 Bytes
None
N/A
Length = 32 Bytes
Memory Write
0111
Locked Access
All combinations
Locked PCI access
As Applicable
Reserved Encodings
All Combinations
None
N/A
EA Memory Access
Address 4GB
None
N/A
Note: N/A refers to a function that is not applicable; Not Supported refers to a function that is available but specifically not
implemented on the North Bridge/Cluster.
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