82443MX Datasheet, PDF (24/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Table 4. IDE Signal Description
Signal
Type
Description
PDA[2:0]
O
IDE Device Address. These output signals are connected to the corresponding
signals on the IDE connectors. They are used to indicate which byte in either the
ATA command block or control block is being addressed.
PDCS1#
O
IDE Device Chip Selects for 100 Range. For ATA Command Register block.
This output signal is connected to the corresponding signal on the IDE connector.
PDCS3#
O
IDE Device Chip Select for 300 Range. For ATA Control Register block. This
output signal is connected to the corresponding signal on the IDE connector.
PDD[15:0]
I/O
IDE Device Data. These signals directly drive the corresponding signals on the
IDE connector.
PDDAK#
O
IDE Device DMA Acknowledge. This signal directly drives the DAK# signal on
the IDE connectors. It is asserted by the 440MX to indicate to IDE DMA slave
devices that a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a
DMA data transfer cycle. This signal is used in conjunction with the PCI bus
master IDE function and is not associated with any AT-compatible DMA channel.
PDDRQ
I
IDE Device DMA Request. This input signal is directly driven from the DREQ
signal on the IDE connector. It is asserted by the IDE device to request a data
transfer. This signal is used in conjunction with the PCI bus master IDE function
and is not associated with any AT-compatible DMA channel.
PDIOR#
O
(PDWSTB /
PRDMARDY#)
Disk I/O Read (PIO and Non-Ultra33 DMA). This is the command to the IDE
device that it may drive data onto the PDD lines. Data is latched by the 440MX
on the de-assertion edge of PDIOR#. The IDE device is selected either by the
ATA Register file chip selects (PDCS1#, PDCS3#) and the PDA lines, or the IDE
DMA acknowledge (PDDAK#).
Disk Write Strobe (Ultra33 DMA Writes to Disk). This is the data write strobe for
writes to disk. When writing to disk, the 440MX drives valid data on rising and
falling edges of PDWSTB.
Disk DMA Ready (Ultra33 DMA Reads from Disk). This is the DMA ready for
reads from disk. When reading from disk, the 440MX de-asserts PRDMARDY#
to pause burst data transfers.
PDIOW#
O
Disk I/O Write (PIO and Non-Ultra33 DMA). This is the command to the IDE
(PDSTOP)
device that it may latch data from the PDD lines. The IDE device latches data on
the de-assertion edge of PDIOW#. The IDE device is selected either by the ATA
Register file chip selects (PDCS1#, PDCS3#) and the PDA lines, or the IDE DMA
acknowledge (PDDAK#).
Disk Stop (Ultra33 DMA). The 440MX asserts this signal to terminate a burst.
PIORDY
I
I/O Channel Ready (PIO). This signal keeps the strobe active (PDIOR# on
reads, PDIOW# on writes) longer than the minimum width. It adds wait states to
PIO transfers.
Disk Read Strobe (Ultra33 DMA Reads from Disk). When reading from disk, the
440MX latches data on rising and falling edges of this signal.
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