82443MX Datasheet, PDF (151/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.12.4.1 PIORDY Masking
When the IDETIMx[IE0] or IDETIMx[IE1] bits are ‘0” the external PIORDY signal is ignored and the internal
PIORDY signal is assumed asserted at the first ISP sample point.
7.12.4.2 PIO 32-Bit IDE Data Port Accesses
A 32-bit PCI transaction run to the IDE data address results in two back-to-back 16-bit transactions to the IDE
data port. The 32-bit data port feature is enabled for all timings, not just enhanced timing. For compatible
timings, a shutdown and startup latency is incurred between the two 16-bit halves of the IDE transaction. This
guarantees that the chip selects will be negated for at least two PCI clocks between the two cycles.
7.12.4.3 PIO IDE Data Port Prefetching and Posting
The 440MX can be programmed via the IDETIM Registers to allow data to be posted to and prefetched from
the IDE data ports. Data prefetching is initiated when a data port read occurs. The read prefetch eliminates
latency to the IDE data ports and allows them to perform back-to-back for the highest possible PIO data
transfer rates. The first data port read of a sector is called the demand read. Subsequent data port reads
from the sector are called prefetch reads. The demand read and all prefetch reads must be of the same size
(16 or 32 bits).
Data posting is performed for writes to the IDE data ports. The transaction is completed on the PCI bus after
the data is received by the 440MX. The 440MX then runs the IDE cycle to transfer the data to the drive. If the
440MX write buffer is non-empty and an unrelated (non-data) IDE transaction occurs, that transaction will be
stalled until all current data in the write buffer is transferred to the drive.
7.12.5 BUS MASTER FUNCTION
The IDE interface integrated in the 440MX can act as a PCI bus master on behalf of an IDE slave device. By
performing an IDE data transfer as a PCI bus master, the 440MX off-loads the CPU and improves system
performance in multitasking environments.
7.12.5.1 Physical Region Descriptor Format
The physical memory region to be transferred during a data transfer is described by a Physical Region
Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory. The data transfer
proceeds until all regions described by the PRDs in the table have been transferred. Note that the 440MX bus
master IDE function does not support memory regions or Descriptor tables located on the X-bus.
Descriptor tables must be aligned on 64-Kbyte boundaries. Each PRD entry in the table is eight bytes in
length. The first four bytes specify the byte address of a physical memory region, which must be Dword-
aligned and cannot cross a 64-Kbyte boundary. The next two bytes specify the size or transfer count of the
region in bytes (64-Kbyte limit per region). A value of zero in these two bytes indicates 64K (thus the
minimum transfer count is 1). If bit 7 (EOT) of the last byte is a 1, it indicates that this is the final PRD in the
Descriptor table. Bus master operation terminates when the last descriptor has been retired. Figure 24
illustrates the physical region descriptor table entries.
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