82443MX Datasheet, PDF (103/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.6.2.1.2 BLOCK TRANSFER MODE
In Block Transfer mode, the DMA is activated by DREQ to continue making transfers during the service until a
Terminal Count (TC), caused by a byte/word count going to FFFFh, is encountered. DREQ must be held
active only until DACK# becomes active. If the channel has been programmed for it, an autoinitialization
occurs at the end of the service. In this mode, it is possible to lock out other devices for a period of time if the
transfer count is programmed to a large number.
Note that block mode transfers are not supported with type-F DMA.
7.6.2.1.3 DEMAND TRANSFER MODE
In Demand Transfer mode, the DMA channel is programmed to continue making transfers until a TC is
encountered, or until the DMA I/O device releases DREQ. Thus, transfers may continue until the I/O device
has exhausted its data capacity. After the I/O device catches up, the DMA service is re-established when the
DMA I/O device reasserts the channel's DREQ. During the time between services when the system is allowed
to operate, the intermediate values of address and byte/word counts are stored in the DMA controller Current
Address and Current Byte/Word Count Registers. A TC can cause an autoinitialize at the end of the service, if
the channel has been programmed for it.
7.6.2.1.4 CASCADE MODE
Cascade mode is not supported.
7.6.2.2 DMA Transfer Types
Each of the three active transfer modes (Single, Block, or Demand) can perform three different types of
transfers: Read, Write and Verify.
7.6.2.2.1 READ TRANSFERS
Read transfers move data from the system DRAM to an X-bus I/O device. The 440MX activates the IOW#
command and the appropriate DRAM memory control signals to indicate a memory read. When the cycle
involves DRAM, the PCI read transaction is initiated as soon as the DMA address is valid.
7.6.2.2.2 WRITE TRANSFERS
Write transfers move data from an I/O device to memory located in system DRAM. For transfers using
compatible timing, the PCI transfer is initiated after the data is valid on the X-bus. The DMA device (I/O
device) is an 8-bit device located on the X-bus.
7.6.2.2.3 VERIFY TRANSFER
Verify transfers are pseudo transfers. The DMA controller generates these addresses as in normal read or
write transfers. However, the 440MX does not activate the X-bus I/O control lines. Only the DACK# lines go
active. The 440MX asserts the appropriate DACK# signal for nine SYSCLKs. If Verify transfers are repeated
during Block or Demand DMA requests, each additional pseudo transfer adds eight SYSCLKs. The DACK#
lines are not toggled for repeated transfers.
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