82443MX Datasheet, PDF (50/173 Pages) Intel Corporation – PCIset

82443MX PCIset
5.
POWER PLANES
5.1 Overview
Table 29 provides an overview of the four main power planes for the 440MX.
Plane
I/O, Core
Resume
RTC
Table 29. Power Planes
Voltage
This plane is powered by the main battery. Assumed to be 3.3V. When the system is
in the S4, S5 or G3 state, this plane is assumed to be shut. In S3, this plane is still
powered.
This plane is powered by either the main battery or the AC power.
This plane is powered by the RTC battery. When other power is available (from the
main battery), external diode coupling provides power to reduce RTC battery drainage.
This plane is assumed to operate from 3.3V down to 2.0V.
5.2 RTC Power Plane
Table 30 lists the RTC power plane signals. These signals must be powered to maintain the system in the
Soft Off state.
Signal
PWROK
RSMRST#
RTCX1, X2
Table 30. RTC Well Signals
Usage
Input indicates that the STR power plane is OK. Used to isolate the RTC and
RESUME wells from the MAIN well.
Input indicates that the Resume well should reset and that the RTC well should
isolate from the Resume Well.
Connections to the 32.768 KHz Crystal.
5.3 Resume Power Plane
Table 31 lists the signals that reside in the Resume well. These signals must be powered to maintain the
system in all states, except the Mechanical Off state.
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