82443MX Datasheet, PDF (127/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.9.5 LOCKABLE RAM RANGES
The real-time clock battery-backed RAM supports two 8-byte ranges that can be enabled via the configuration
space. If the configuration bits are set, the corresponding range in the RAM is not readable or writeable. A
write cycle to those locations has no effect. A read cycle to those locations does not return the actual location
value.
Once enabled, this function can only be disabled by a hard reset.
7.9.6 RTC EXTERNAL CONNECTIONS
7.9.6.1 RTC Crystal
The RTC module requires an externally connected crystal on the RTCX1 and RTCX2 pins.
7.9.6.2 RTC Battery
The RTC module requires an external battery connection to maintain the RTC block while the 440MX is not
powered by the system.
The battery must also be connected to the 440MX via isolation diodes. This is both a chip-design
requirement, as well as a UL requirement. The diode circuit allows the RTC well to be powered by the battery
when system power is not available, but by the system power when it is available. This is done by setting the
diode to be reverse-biased when system power is not available.
7.9.7 CENTURY ROLLOVER
The Year Register only reports a value of 00 to 99. In the year 2000, this will roll over to 00, however this
could be misinterpreted as 1900, not 2000. The NEWCENTURY_STS bit records this rollover. This bit is in
the RTC well in the General Purpose Event1 Status Register (PMBASE + 38, bit 12 System I/O space).
When the system is in the active state and a century rollover occurs, the NEWCENTURY_STS bit is set,
which causes an SMI to be generated. The SMI handler then checks the NEWCENTURY_STS bit and finds it
to be set, in which case, it increments the top two digits of the year (Location 32h) in the RTC RAM.
In case the system is in the S1-S5 states, the century rollover also causes the NEWCENTURY_STS (RTC
well) bit to be set. A wake event does not occur. Once the system awakens (for some other reason), the BIOS
finds the NEWCENTURY_STS bit set and generates an SMI. The SMI handler then changes (increments) the
year byte in the RTC RAM.
7.10 Interrupt Controller
The 440MX contains an ISA-compatible interrupt controller that incorporates the functionality of two 82C59
interrupt controllers. The Interrupt Registers control the operation of the interrupt controller and can be
accessed from the PCI bus via the PCI I/O space. In addition, some of the registers can be accessed from the
ISA bus via the ISA I/O space.
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