82443MX Datasheet, PDF (150/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Enhanced timing data port
2
2-5
1-4
2
Note: Command strobe widths are in PCI clock units.
NOTE:
Startup and Recovery latencies are incurred for all IDE PIO transactions, EXCEPT enhanced timing
data port transactions. Further, the IDE chip selects are guaranteed to be de-asserted for at least two
clocks after the de-assertion of the I/O strobe for the last transaction and before the Startup latency of
the next.
7.12.4 ENHANCED TIMING MODES
The IDE interface implemented by the 440MX includes fast timing modes that target local bus
implementations. These timing modes are faster than those possible with ISA-based implementations and are
controlled with the granularity of the PCI clock.
The fast timing modes may be enabled only for the IDE data ports. All other transactions to the IDE registers
are run in single transaction mode with compatible timings.
Up to two IDE devices may be attached to the IDE connector (drive 0 and drive 1). The timing mode for the
drives is selected via several registers.
When the IDETIMx[SITRE] bit is disabled, one fast timing mode can be applied to one or both drives by
programming the IDETIMx[ISP] and IDETIMx[RCT] fields as shown in Table 77. Fast Timing mode may be
applied to drive 0, drive 1, or both, by setting the IDETIMx[TIME0] and/or the IDETIMx[TIME1] bits.
Transactions targeting the other drive use compatible timing. When the IDETIMx[SITRE] bit is enabled, a fast
timing mode can be selected for each drive by programming the IDETIMx and SIDETIM Registers. Table 77
identifies how these bits can be programmed for Drive 0 and Drive 1 timing mode selection.
IDETIMx
[SITRE]
0
0
0
0
1
1
1
1
Table 77. IDETIMx Timing Modes for Drives 0 and 1
IDETIMx
[TIME0]
IDETIMx
[TIME1]
Drive 0
Timing
Drive 1
Timing
0
0
Compatible
Compatible
0
1
Compatible
IDETIMx[ISP/RCT]
1
0
IDETIMx[ISP/RCT]
Compatible
1
1
IDETIMx[ISP/RCT]
IDETIMx[ISP/RCT]
0
0
Compatible
Compatible
0
1
Compatible
SIDETIM[ISP/RCT]
1
0
IDETIMx[ISP/RCT]
Compatible
1
1
IDETIMx[ISP/RCT]
SIDETIM[ISP/RCT]
The synchronous DMA timing mode can also be applied independently to each drive by programming the
SDMAC and SDMATIM Registers. When a particular drive is programmed for Sync DMA mode (SYNCDMA
and SDMATIM Registers) AND a fast timing mode (IDETIMx or SIDETIM Register), DMA transfers are
processed using the Sync DMA timing mode and PIO transfers are processed using the fast timing mode.
138