82443MX Datasheet, PDF (6/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.6.2.6
Software Commands................................................................................. 96
7.6.2.7
Terminal Count Summary ......................................................................... 96
7.6.2.8
X-bus Refresh Cycles ............................................................................... 97
7.7 PCI DMA ...................................................................................................................................... 97
7.7.1 Overview......................................................................................................................... 97
7.7.1.1
PC/PCI DMA ............................................................................................. 97
7.7.1.2
Distributed DMA ........................................................................................ 98
7.7.2 Configuration .................................................................................................................. 98
7.7.3 PC/PCI............................................................................................................................ 98
7.7.3.1
Overview................................................................................................... 98
7.7.3.2
Additional Configuration ............................................................................ 98
7.7.3.3
PC/PCI Expansion Protocol ...................................................................... 98
7.7.3.4
PC/PCI Expansion Cycles....................................................................... 100
7.7.4 Dstributed DMA ............................................................................................................ 101
7.7.4.1
Overview................................................................................................. 101
7.7.4.2
Additional Configuration .......................................................................... 101
7.7.4.3
Read/Write Cycle Protocols .................................................................... 102
7.7.4.4
Calculating the I/O Address..................................................................... 106
7.7.4.5
Power Management Implications ............................................................ 108
7.7.4.6
Other Clarifications.................................................................................. 108
7.8 Timer .......................................................................................................................................... 108
7.8.1 Counter/Timers ............................................................................................................. 108
7.8.1.1
Counter 0, System Timer ........................................................................ 109
7.8.1.2
Counter 1, Refresh Request Signal ......................................................... 109
7.8.1.3
Counter 2, Speaker Tone ........................................................................ 109
7.8.2 Interval Timer Address Map .......................................................................................... 109
7.8.3 Programming the Interval Timer.................................................................................... 110
7.8.3.1
Write Operations ..................................................................................... 111
7.8.3.2
Interval Timer Control Word Format ........................................................ 111
7.8.3.3
Counter Latch Command ........................................................................ 112
7.9 RTC............................................................................................................................................ 113
7.9.1 RTC Overview .............................................................................................................. 113
7.9.2 RTC Registers and RAM............................................................................................... 114
7.9.3 RTC Update Cycle ........................................................................................................ 114
7.9.4 RTC Interrupts .............................................................................................................. 114
7.9.5 Lockable RAM Ranges ................................................................................................. 115
7.9.6 RTC External Connections............................................................................................ 115
7.9.6.1
RTC Crystal ............................................................................................ 115
vi