82443MX Datasheet, PDF (94/173 Pages) Intel Corporation – PCIset

82443MX PCIset
The AC-link protocol provides for a special 16-bit2 time slot (Slot 0) wherein each bit conveys a valid tag for its
corresponding time slot within the current audio frame. A “1” in a given bit position of Slot 0 indicates that the
corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid
data. If a slot is “tagged” invalid, it is the responsibility of the source of the data, (AC’97 for the input stream
and AC’97 controller for the output stream), to stuff all bit positions with 0’s during that slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of
the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the audio frame where
SYNC is low is defined as the “Data Phase”.
Slot #
SYNC
OUTGOING STREAMS
INCOMING STREAMS
Tag Phase
0 1 2 3 4 5 6 7 8 9 10 11 12
TAG
CMD
ADR
CMD
DATA
PCM
LEFT
TAG
STATUS STATUS
ADR DATA
PCM
LEFT
PCM
RIGHT
PCM
RIGHT
MDM
CDC
MDM
CDC
RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD ^I/O
Control
MIC RSRVD RSRVD RSRVD RSRVD RSRVD ^I/O
Status
Data Phase
Figure 10. AC’97 Standard Bi-directional Audio Frame
7.5 PCI Interface
7.5.1 PCI INTERFACE OVERVIEW
The 440MX PCI bus interface is compliant with the PCI Local Bus Specification, Revision 2.2. The
implementation is optimized for high-performance data streaming when the 440MX is acting as either the
target or the initiator on the PCI bus.
The 440MX integrates the traditional North and South Bridges/Clusters with additional features into a single
chip with the point of integration being the PCI bus (see Figure 11). This bus is routed out to the chip
interface and forms the PCI interface to the external PCI devices.
2 _{13 bits defined, with three reserved trailing bit positions.}
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