82443MX Datasheet, PDF (133/173 Pages) Intel Corporation – PCIset

82443MX PCIset
4. The slave mode address is set to 7.
5. Special Mask Mode is cleared and Status Read is set to IRR.

ICW2 is programmed to provide bits [7:3] of the interrupt vector that is released onto the data bus by the
interrupt controller during an interrupt acknowledge. A different base [7:3] is selected for each interrupt
controller. Suggested default values for a typical ISA system are listed in Table 72.

ICW3 is programmed differently for CNTRL-1 and CNTRL-2, and has a different meaning for each
controller.
For CNTRL-1, the master controller, ICW3 is used to indicate which IRQx input line is used to cascade
CNTRL-2, the slave controller. Within the 440MX interrupt unit, IRQ2 on CNTRL-1 is used to cascade the
INTR output of CNTRL-2. Consequently, bit-2 of ICW3 on CNTRL-1 is set to a 1, and the other bits are
set to 0's.
For CNTRL-2, ICW3 is the slave identification code used during an interrupt acknowledge cycle. CNTRL-
1 broadcasts a code to CNTRL-2 over three internal cascade lines if an IRQ[x] line from CNTRL-2 won
the priority arbitration on the master controller and was granted an interrupt acknowledge by the CPU.
CNTRL-2 compares this identification code to the value stored in ICW3, and if the code is equal to bits
[2:0] of ICW3, CNTRL-2 assumes responsibility for broadcasting the interrupt vector during the second
interrupt acknowledge cycle pulse.

ICW4 must be programmed on both controllers. At the very least, bit 0 must be set to 1 to indicate that
the controllers are operating in an Intel Architecture-based system.
Table 72 lists the typical values programmed by the BIOS at power-up for the 440MX interrupt controller.
Figure 17 illustrates the sequence the software must follow to load the ICWs. The sequence must be
executed for CNTRL-1 and CNTRL-2. ICW1, ICW2, ICW3, and ICW4 must be written in order. Any
divergence from this sequence, such as an attempt to program an OCW, will result in improper initialization of
the interrupt controller and unexpected, erratic system behavior. It is suggested that CNTRL-2 be initialized
first, followed by CNTRL-1.
In the 440MX, it is required that all four ICWs be initialized.
Table 72. Suggested Default Values for ICW Registers
Port
Value
Contents
020h
11h
CNTLR-1, ICW1
021h
08h
CNTLR-1, ICW2 Vector Address for 000020h
021h
04h
CNTLR-1, ICW3 Indicates Slave Connection
021h
01h
CNTLR-1, ICW4 8086 Mode
021h
B8h
CNTLR-1, Interrupt Mask (may vary)
0A0h
11h
CNTLR-2, ICW1
0A1h
70h
CNTLR-2, ICW2 Vector Address for 0001C0h
0A1h
02h
CNTLR-2, ICW3 Indicates Slave ID
0A1h
01h
CNTLR-2, ICW4 8086 Mode
0A1h
BDh
CNTLR-2, Interrupt Mask (may vary)
121