82443MX Datasheet, PDF (21/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Signal
HIT#
HITM#
HLOCK#
HREQ(4:0)#
HTRDY#
IGNNE#
INIT#
INTR
Type
Description
I/O
Hit. Indicates that a caching agent holds an unmodified version of the requested
line. Also driven in conjunction with HITM# by the target to extend the snoop
window.
I/O
Hit Modified. Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line.
Also, driven in conjunction with HIT# to extend the snoop window.
I/O
Host Lock. All processor cycles sampled with the assertion of HLOCK# and
ADS#, until the negation of HLOCK# must be atomic, i.e., no PCI snoopable
access to DRAM is allowed when HLOCK# is asserted by the processor.
I/O
Request Command. Asserted during both clocks of a request phase. In the first
clock, the signals define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second clock, the signals carry additional
information to define the complete transaction type. The transactions supported
by the 440MX Host Bridge are defined in Section 7.1.
I/O
Host Target Ready. Indicates that the target of the processor transaction is
ready to enter the data transfer phase.
OD Ignore Numeric Error. This signal is connected to the ignore error pin on the
processor. IGNNE# is only used if the 440MX coprocessor error reporting
function is enabled in the XBCSA Register (bit 5=1). If FERR# is active, indicating
a coprocessor error, a write to the Coprocessor Error Register (F0h) causes the
IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If
FERR# is not asserted when the Coprocessor Error Register is written, the
IGNNE# signal is not asserted.
OD Initialization. INIT# is asserted in response to any one of the following
conditions:

When the System Reset bit in the Reset Control Register is reset to 0 and the
Reset CPU bit toggles from 0 to 1, the 440MX initiates a soft reset by
asserting INIT#.

If a Shut Down Special cycle is decoded on the PCI Bus.

If the RCIN# signal is asserted.

If a write occurs to Port 92h, bit 0.
When asserted, INIT# remains asserted for approximately 64 PCI clocks before
being negated.
Mobile Celeron processor / Pentium II Processor:
During Reset: High
After Reset: High During POS: High
OD CPU Interrupt. INTR is driven by the 440MX to signal the CPU that an interrupt
request is pending and needs to be serviced. It is asynchronous with respect to
SYSCLK or PCICLK and is always an output. The interrupt controller must be
programmed following PCIRST# to ensure that INTR is at a known state.
During Reset: Low
After Reset: Low During POS: Low
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